Datasheet

Section 4 Exception Handling
Page 116 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
φ
RES, MRES
Address bus
RD
HWR, LWR
D15 to D0
(1) (3)
High
(2) (4)
(5)
(6)
* * *
Vector
fetch
Internal
processing
Prefetch of first program
instruction
(1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000*,
(3) = H'000002; when manual reset, (1)= H'000004, (3)= H'000006)
(2) (4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2) (4))
(6) First program instruction
Note: * 3 program wait states are inserted.
Figure 4.2 Reset Sequence (Modes 4 and 5)