Datasheet

Page xviii of lvi R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
Item Page Revision (See Manual for Details)
2.8.1 Overview
Figure 2.14
Processing States
86 Figure amended
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, trace, interrupt,
or trap instruction.
2.8.3 Exception-
Handling State
88 Descriptioon amended
The exception-handling state is a transient state that occurs when
the CPU alters the normal processing flow due to a reset, trace,
interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that
address.
4.1.1 Exception
Handling Types and
Priority
111 Descriptioon amended
As table 4.1 indicates, exception handling may be caused by a
reset, trace, direct transition, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or
more exceptions occur simultaneously, they are accepted and
processed in order of priority. Trap instruction exceptions are
accepted at all times, in the program execution state.
4.7 Notes on Use
of the Stack
Figure 4.6
Operation when SP
Value is Odd
122 Figure amended
SP
SP
SP
CCR
PC
R1L
PC
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFE
H'FFFEFF
MOV.B R1L, @–ER7TRAPA instruction executed
7.5.8 Wait Control
Figure 7.17
Example Program
Wait Insertion Timing
(Wait 2 State
Insertion)
217 Figure amended
Note:
n = 2 to 5