Datasheet

Section 5 Interrupt Controller
Page 126 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
MRESE
0
R/W
1
—
0
—
Bit
Initial value
R/W
:
:
:
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control
Register (SYSCR).
SYSCR is initialized to H'01 by a power-on reset, manual reset, and in hardware standby mode.
SYSCR is not initialized in software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5 Bit 4
INTM1 INTM0
Interrupt
Control Mode Description
0 0 0 Interrupts are controlled by I bit (Initial value)
1 — Setting prohibited
1 0 2 Interrupts are controlled by bits I2 to I0, and IPR
1 — Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG Description
0 Interrupt request generated at falling edge of NMI input (Initial value)
1 Interrupt request generated at rising edge of NMI input