Datasheet

Section 5 Interrupt Controller
R01UH0166EJ0600 Rev. 6.00 Page 127 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO)
7
—
0
—
6
IPR6
1
R/W
5
IPR5
1
R/W
4
IPR4
1
R/W
3
—
0
—
0
IPR0
1
R/W
2
IPR2
1
R/W
1
IPR1
1
R/W
Bit
Initial value
R/W
:
:
:
The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5.3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.
Table 5.3 Correspondence between Interrupt Sources and IPR Settings
Bits
Register 6 to 4 2 to 0
IPRA IRQ0 IRQ1
IPRB IRQ2
IRQ3
IRQ4
IRQ5
IPRC IRQ6
IRQ7
DTC
*
IPRD Watchdog timer 0 Refresh timer
*
IPRE PC break
*
A/D converter, watchdog timer 1
*
IPRF TPU channel 0 TPU channel 1
IPRG TPU channel 2 TPU channel 3
IPRH TPU channel 4 TPU channel 5
IPRI 8-bit timer channel 0
*
8-bit timer channel 1
*
IPRJ DMAC
*
SCI channel 0
IPRK SCI channel 1 SCI channel 2
IPRL 8-bit timer 2, 3
*
IIC (Option)
*
IPRO SCI channel 3 SCI channel 4
Note: * This function is not available in the H8S/2695.