Datasheet

Section 5 Interrupt Controller
R01UH0166EJ0600 Rev. 6.00 Page 129 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCRH
15
IRQ7SCB
0
R/W
14
IRQ7SCA
0
R/W
13
IRQ6SCB
0
R/W
12
IRQ6SCA
0
R/W
11
IRQ5SCB
0
R/W
8
IRQ4SCA
0
R/W
10
IRQ5SCA
0
R/W
9
IRQ4SCB
0
R/W
Bit
Initial value
R/W
:
:
:
ISCRL
7
IRQ3SCB
0
R/W
6
IRQ3SCA
0
R/W
5
IRQ2SCB
0
R/W
4
IRQ2SCA
0
R/W
3
IRQ1SCB
0
R/W
0
IRQ0SCA
0
R/W
2
IRQ1SCA
0
R/W
1
IRQ0SCB
0
R/W
Bit
Initial value
R/W
:
:
:
The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or
both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and
B (IRQ0SCA, IRQ0SCB)
Bits 15 to 0
IRQ7SCB to
IRQ0SCB
IRQ7SCA to
IRQ0SCA Description
0 0 Interrupt request generated at IRQ7 to IRQ0 input low level
(initial value)
1 Interrupt request generated at falling edge of IRQ7 to IRQ0 input
1 0 Interrupt request generated at rising edge of IRQ7 to IRQ0 input
1 Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input