Datasheet

Page xx of lvi R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
Item Page Revision (See Manual for Details)
11.1.1 Features 543 Description amended
• Cascaded operation
⎯ Channel 1 (channel 4) input clock operates as 32-bit
counter by setting channel 2 (channel 5) overflow/underflow
18.3.5 Slave
Receive Operation
878 Description added
In slave receive mode, the master device outputs the transmit
clock and transmit data, and the slave device returns an
acknowledge signal.
The slave device compares its own address with the slave address
in the first frame following the establishment of the start condition
issued by the master device. If the addresses match, the slave
device operates as the slave device designated by the master
device.
Figure 18.14 is a flowchart showing an example of slave receive
mode operation.
Figure 18.14
Flowchart for Slave
Receive Mode
(Example)
879 Figure added
18.3.6 Slave
Transmit Operation
883 Description added
In slave transmit operation, the slave device compares its own
address with the slave address transmitted by the master device in
the first frame (address receive frame) following detection of the
start condition. If the addresses match and the 8th bit (R/W) is set
to 1 (read), the TRS bit in ICCR is automatically set to 1 and slave
transmit mode is activated.
Figure 18.17 is a flowchart showing an example of slave transmit
mode operation.
Figure 18.17
Flowchart for Slave
Transmit Mode
(Example)
Figure added
18.3.10 Sample
Flowcharts
⎯ Description deleted
18.4 Usage Notes
Table 18.6 I
2
C Bus
Timing (SCL and
SDA Output)
891 Table amended
Data output setup time (master)
Data output setup time (slave)
Data output hold time
t
SDASO
t
SDAHO
1t
SCLLO
− 3t
cyc
1t
SCLL
− (6t
cyc
or 12t
cyc
*)
3t
cyc
ns
ns
Figure 25.33,
figure 26.33
(reference)
Item Symbol Output Timing Unit
Notes