Datasheet

Section 5 Interrupt Controller
Page 150 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
5.4.4 Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
(14)(12)(10)(8)
(6)(4)(2)
(1) (5)
(7) (9) (11) (13)
Interrupt service routine instruction prefetch
Internal operation
Vector fetchStack
Instruction prefetch
Internal operation
Interrupt acceptance
Interrupt level determination Wait for end of instruction
Interrupt request signal
Internal address bus Internal read signal Internal write signal Internal data us
φ
(3)
(1) (2) (4) (3) (5) (7)
Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4
Saved PC and saved CCR Vector address Interrupt handling routine start address (vector address contents) Interrupt handling routine start address ((13) = (10) (12)) First instruction of interrupt handling routine
(6) (8) (9) (11) (10) (12) (13) (14)
Figure 5.7 Interrupt Exception Handling