Datasheet

R01UH0166EJ0600 Rev. 6.00 Page xxi of lvi
Mar 02, 2011
Item Page Revision (See Manual for Details)
18.4 Usage Notes
Table 18.8 I
2
C Bus
Timing (with
Maximum Influence
of t
Sr
/t
Sf
)
893 Table amended
t
SDASO
(master)
1t
SCLLO
*
3
−3t
cyc
(−t
Sr
)
Item
t
cyc
Indication
t
Sr
/t
Sf
Influence
(Max.)
I
2
C Bus
Specifi-
cation
(Min.)
Time Indication (at Maximum Transfer Rate) [ns]
φ =
5 MHz
φ =
8 MHz
φ =
10 MHz
φ =
16 MHz
φ =
20 MHz
φ =
25 MHz
φ =
28 MHz
t
SDASO
(slave)
1t
SCLL
*
3
−12t
cyc
*
2
(−t
Sr
)
Standard
mode
−1000
−300
−1000
−300
250
100
250
100
3100
400
3100
400
3325
625
3325
625
3400
700
3400
700
3513
813
3513
813
3550
850
3550
850
3580
880
3580
880
3593
893
3593
893
High-speed
mode
Standard
mode
High-speed
mode
Notes amended
Notes 2. Value when the IICX bit is set to 1. When the IICX bit is
cleared to 0, the value is (1t
SCLL
– 6t
cyc
).
3. Calculated using the I
2
C bus specification values
(standard mode: 4700 ns min.; high-speed mode: 1300
ns min.).
902 Description added
• Notes on Wait Operation in Master Mode
During master mode operation using the wait function, when
the interrupt flag IRIC bit is cleared from 1 to 0 between the
falling edge of the 7th clock cycle and the falling edge of the
8th clock cycle, in some cases no wait is inserted after the
falling edge of the 8th clock cycle and the clock pulse of the 9th
clock cycle is output continuously.
Observe the following with regard to clearing the IRIC flag
while using the wait function.
At the rising edge of the 9th clock cycle, set the IRIC flag to 1
and then clear it to zero before the rising edge of the 1st clock
cycle (while the value of the BC2 to BC0 counter value is 2 or
greater).
If clearing of the IRIC flag is delayed by interrupt processing or
the like and the BC counter value reaches 1 or 0, confirm that
the SCL pin state is low-level after the BC2 to BC0 counter has
reached 0 and then clear the IRIC flag. (See figure 18.28.)
Figure 18.28
Timing of IRIC Flag
Clearing During Wait
Operation
Figure added