Datasheet

Section 5 Interrupt Controller
Page 156 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
5.6.2 Block Diagram
Figure 5.9 shows a block diagram of the DTC and DMAC interrupt controller.
DMAC
*
Selection
circuit
DTCER
DTVECR
Control logic
Determination of
priority
CPU
DTC
*
Select
signal
IRQ
interrupt
On-chip
supporting
module
Disenable signal
Clear signal
Clear signal
Interrupt controller
I, I2 to I0
Interrupt source
clear signal
Interrupt
request
DTC activation
request vector
number
CPU interrupt
request vector
number
SWDTE
clear signal
Clear signal
Note: * This function is not available in the H8S/2695.
Figure 5.9 Interrupt Control for DTC
*
and DMAC
*