Datasheet

Section 5 Interrupt Controller

R01UH0166EJ0600 Rev. 6.00 Page 157 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

5.6.3 Operation (DMAC and DTC functions are not available in the H8S/2695)

The interrupt controller has three main functions in DTC and DMAC control.

(1) Selection of Interrupt Source: DMAC inputs activation factor directly to each channel. The

activation factors for each channel of DMAC are selected by DTF3 to DTF0 bits of DMACR. The

DTA bit of DMABCR can be used to select whether the selected activation factors are managed

by DMAC. By setting the DTA bit to 1, the interrupt factor which were the activation factor for

that DMAC do not act as the DTC activation factor or the CPU interrupt factor.

Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation

request or CPU interrupt request by the DTCERA to DTCERF of DTC and the DTCE bit of

DTCERI.

By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after

DTC data transfer, and request a CPU interrupt.

If DTC carries out the designate number of data transfers and the transfer counter reads 0, after

DTC data transfer, the DTCE bit is also cleared to 0, and a CPU interrupt requested.

(2) Determination of Priority: The DTC activation source is selected in accordance with the

default priority order, and is not affected by mask or priority levels. See section 8.6, Interrupts,

and section 9.3.3, DTC Vector Table for the respective priority.

(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU

interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception

handling.

If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or

CPU interrupt factor, these operate independently. They operate in accordance with the respective

operating states and bus priorities.

Table 5.11 shows the interrupt factor clear control and selection of interrupt factors by

specification of the DTA bit of DMAC's DMABCR, DTC's DTCERA to DTCERF, DTCERI's

DTCE bits, and the DISEL bit of DTC's MRB.