Datasheet

Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695)
Page 162 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
6.2.3 Break Control Register A (BCRA)
Bit :
Initial value :
R/W :
Note: * Only 0 can be written, for flag clearing.
R/(W)*
0
CMFA
7
R/W
0
CDA
6
R/W
0
BAMRA2
5
R/W
0
BAMRA1
4
R/W
0
BAMRA0
3
R/W
0
CSELA1
2
R/W
0
CSELA0
1
R/W
0
BIEA
0
BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects
the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)
specifies whether the break condition is applied to an instruction fetch or a data access. It also
contains a condition match flag.
BCRA is initialized to H'00 by a power-on reset and in hardware standby mode.
Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is
satisfied. This flag is not cleared to 0.
Bit 7
CMFA Description
0 [Clearing condition]
When 0 is written to CMFA after reading CMFA = 1 (Initial value)
1 [Setting condition]
When a condition set for channel A is satisfied
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus
master.
Bit 6
CDA Description
0 PC break is performed when CPU is bus master (Initial value)
1 PC break is performed when CPU or DTC is bus master
Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2–BAMRA0): These bits
specify which bits of the break address (BAA23 to BAA0) set in BARA are to be masked.