Datasheet

Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 163 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 5 Bit 4 Bit 3
BAMRA2 BAMRA1 BAMRA0 Description
0 0 0 All BARA bits are unmasked and included in break conditions
(Initial value)
1 BAA0 (lowest bit) is masked, and not included in break
conditions
1 0 BAA1 to BAA0 (lower 2 bits) are masked, and not included in
break conditions
1 BAA2 to BAA0 (lower 3 bits) are masked, and not included in
break conditions
1 0 0 BAA3 to BAA0 (lower 4 bits) are masked, and not included in
break conditions
1 BAA7 to BAA0 (lower 8 bits) are masked, and not included in
break conditions
1 0 BAA11 to BAA0 (lower 12 bits) are masked, and not included in
break conditions
1 BAA15 to BAA0 (lower 16 bits) are masked, and not included in
break conditions
Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits selection an
instruction fetch, data read, data write, or data read/write cycle as the channel A break condition.
Bit 2 Bit 1
CSELA1 CSELA0 Description
0 0 Instruction fetch is used as break condition (Initial value)
1 Data read cycle is used as break condition
1 0 Data write cycle is used as break condition
1 Data read/write cycle is used as break condition
Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts.
Bit 0
BIEA Description
0 PC break interrupts are disabled (Initial value)
1 PC break interrupts are enabled