Datasheet

Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 165 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
6.3 Operation
The operation flow from break condition setting to PC break interrupt exception handling is
shown in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break
Interrupt Due to Data Access, taking the example of channel A.
6.3.1 PC Break Interrupt Due to Instruction Fetch
(1) Initial settings
⎯ Set the break address in BARA. For a PC break caused by an instruction fetch, set the
address of the first instruction byte as the break address.
⎯ Set the break conditions in BCRA.
BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must
be the CPU. Set 0 to select the CPU.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2 to 1 (CSELA1 to CSELA0): Set 00 to specify an instruction fetch as the
break condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
(2) Satisfaction of break condition
⎯ When the instruction at the set address is fetched, a PC break request is generated
immediately before execution of the fetched instruction, and the condition match flag
(CMFA) is set.
(3) Interrupt handling
⎯ After priority determination by the interrupt controller, PC break interrupt exception
handling is started.