Datasheet

Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695)
Page 166 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
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H8S/2633R F-ZTAT
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, H8S/2695
6.3.2 PC Break Interrupt Due to Data Access
(1) Initial settings
⎯ Set the break address in BARA. For a PC break caused by a data access, set the target
ROM, RAM, I/O, or external address space address as the break address. Stack operations
and branch address reads are included in data accesses.
⎯ Set the break conditions in BCRA.
BCRA bit 6 (CDA): Select the bus master.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2 to 1 (CSELA1 to CSELA0): Set 01, 10, or 11 to specify data access as the
break condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
(2) Satisfaction of break condition
⎯ After execution of the instruction that performs a data access on the set address, a PC break
request is generated and the condition match flag (CMFA) is set.
(3) Interrupt handling
⎯ After priority determination by the interrupt controller, PC break interrupt exception
handling is started.
6.3.3 Notes on PC Break Interrupt Handling
(1) The PC break interrupt is shared by channels A and B. The channel from which the request
was issued must be determined by the interrupt handler.
(2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB
after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be
requested after interrupt handling ends.
(3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has
been transferred to the CPU by the bus controller.