Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 171 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Section 7 Bus Controller
7.1 Overview
The H8S/2633 Group has a built-in bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU, DMA controller (DMAC)
*
, and data transfer controller (DTC)
*
.
Note: * This function is not available in the H8S/2695.
7.1.1 Features
The features of the bus controller are listed below.
• Manages external address space in area units
⎯ Manages the external space as 8 areas of 2 Mbytes
⎯ Bus specifications can be set independently for each area
⎯ DRAM/Burst ROM interface can be set
• Basic bus interface
⎯ Chip selects (CS0 to CS7) can be output for areas 0 to 7
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
• DRAM interface
*
⎯ DRAM interface can be set for areas 2 to 5 (in advanced mode)
⎯ Multiplexed output of row and column addresses (8/9/10 bit)
⎯ 2 CAS method
⎯ Burst operation (in high-speed mode)
⎯ Insertion of T
P
cycle to secure RAS precharge time
⎯ Selection of CAS-before-RAS refresh and self refresh
• Burst ROM interface
⎯ Burst ROM interface can be set for area 0
⎯ Choice of 1- or 2-state burst access