Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 173 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the bus controller.
Area decoder
Bus
controller
ABWCR
ASTCR
BCRH
BCRL
Internal
address bus
External bus control signals
CS0 to CS7
Legend:
ABWCR: Bus width control register
ASTCR: Access state control register
BCRH: Bus control register H
BCRL: Bus control register L
WCRH: Wait control register H
WCRL: Wait control register L
MCR
*
:
DRAMCR
*
:
RTCNT
*
:
RTCOR
*
:
Note: * This function is not available in the H8S/2695.
Memory control register
DRAM control register
Refresh timer counter
Refresh time constand register
BREQ
BACK
BREQO
Internal control
signals
Wait
controller
WCRH
WCRL
DRAM controller
External DRAM
control signal
MCR
*
DRAMCR
*
RTCNT
*
RTCOR
*
Bus mode signal
Bus arbiter
CPU bus request signal
DTC
*
bus request signal
DMAC
*
bus request signal
CPU bus acknowledge signal
DTC
*
bus acknowledge signal
DMAC
*
bus acknowledge signal
WAIT
Internal data bus
Figure 7.1 Block Diagram of Bus Controller