Datasheet

Section 7 Bus Controller
Page 174 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.1.3 Pin Configuration
Table 7.1 summarizes the pins of the bus controller.
Table 7.1 Bus Controller Pins
Name Symbol I/O Function
Address strobe AS Output Strobe signal indicating that address output on address
bus is enabled.
Read RD Output Strobe signal indicating that external space is being
read.
High write/
write enable
*
HWR Output Strobe signal indicating that external space is to be
written, and upper half (D15 to D8) of data bus is
enabled. 2CAS method DRAM with enable signal
*
.
Low write LWR Output Strobe signal indicating that external space is to be
written, and lower half (D7 to D0) of data bus is enabled.
Chip select 0 CS0 Output Strobe signal showing selection of area 0
Chip select 1 CS1 Output Strobe signal showing selection of area 1
Chip select 2/row
address strobe 2
*
CS2 Output Strobe signal showing selection of area 2.
When area 2 is allocated to DRAM space, this is the row
address strobe signal for DRAM
*
.
When areas 2 to 5 are contiguous DRAM space, this is
the row address strobe signal for DRAM
*
.
Chip select 3/row
address strobe 3
*
CS3/OE
*
Output Strobe signal showing selection of area 3.
When area 3 is allocated to DRAM space, this is the row
address strobe signal for DRAM
*
.
When only area 2 is allocated to DRAM space, or when
areas 2 to 5 are contiguous DRAM space, this is output
enable signal
*
.
Chip select 4/row
address strobe 4
*
CS4 Output Strobe signal showing selection of area 4.
When area 4 is allocated to DRAM space, this is the row
address strobe signal for DRAM
*
.
Chip select 5/row
address strobe 5
*
CS5 Output Strobe signal showing selection of area 5.
When area 5 is allocated to DRAM space, this is the row
address strobe signal for DRAM
*
.
Chip select 6 CS6 Output Strobe signal showing selection of area 6
Chip select 7 CS7 Output Strobe signal showing selection of area 7
Upper column
address strobe
*
CAS
*
Output 2 CAS method DRAM upper column address strobe
signal
*