Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 175 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Name Symbol I/O Function
Lower column
strobe
*
LCAS
*
Output DRAM lower column address strobe signal
*
Wait WAIT Input Wait request signal when accessing external 3-state
access space.
Bus request BREQ Input Request signal that releases bus to external device.
Bus request
acknowledge
BACK Output Acknowledge signal indicating that bus has been
released.
Bus request output BREQO Output External bus request signal used when internal bus
master accesses external space when external bus is
released.
Note: * This function is not available in the H8S/2695.
7.1.4 Register Configuration
Table 7.2 summarizes the registers of the bus controller.
Table 7.2 Bus Controller Registers
Initial Value
Name Abbreviation R/W
Power-On
Reset
Manual
Reset Address
*
1
Bus width control register ABWCR R/W H'FF/H'00
*
2
Retained H'FED0
Access state control register ASTCR R/W H'FF Retained H'FED1
Wait control register H WCRH R/W H'FF Retained H'FED2
Wait control register L WCRL R/W H'FF Retained H'FED3
Bus control register H BCRH R/W H'D0 Retained H'FED4
Bus control register L BCRL R/W H'08 Retained H'FED5
Pin function control register PFCR R/W H'0D/H'00 Retained H'FDEB
Memory control register MCR
*
3
R/W H'00 Retained H'FED6
DRAM control register DRAMCR
*
3
R/W H'00 Retained H'FED7
Refresh timer counter RTCNT
*
3
R/W H'00 Retained H'FED8
Refresh time constant register RTCOR
*
3
R/W H'FF Retained H'FED9
Notes: 1. Lower 16 bits of the address.
2. Determined by the MCU operating mode.
3. This function is not available in the H8S/2695.