Datasheet

Section 7 Bus Controller
Page 184 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.2.5 Bus Control Register L (BCRL)
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
—
0
—
4
OES
*
0
R/W
3
DDS
*
1
R/W
0
WAITE
0
R/W
2
RCTS
*
0
R/W
1
WDBE
0
R/W
Bit
Initial value
R/W
Note: * This function is not available in the H8S/2695. In writing to OES, DDS, RCTS, the initial
value should be written to these bits.
:
:
:
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized
by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE Description
0 External bus release is disabled. BREQ, BACK and BREQO can be used as I/O ports
(Initial value)
1 External bus release is enabled
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE Description
0 BREQO output disabled. BREQO can be used as I/O port (Initial value)
1 BREQO output enabled
Bit 5—Reserved: This bit cannot be modified and is always read as 0.