Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 187 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 6—CS3/CS6 Select (CSS36): This bit selects the contents of CS output via the PG1 pin. In
modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS.
Bit 6
CSS36 Description
0 Selects CS3 (Initial value)
1 Selects CS6
Bit 5—BUZZ Output Enable (BUZZE): This bit enables/disables BUZZ output via the PF1 pin.
The WDT1 input clock, selected with PSS and CKS2 to CKS0, is output as the BUZZ signal. See
section 15.2.4, Pin Function Control Register (PFCR) for details of BUZZ output.
Bit 5
BUZZE Description
0 Functions as PF1 input pin (Initial value)
1 Functions as BUZZ output pin
Bit 4—LCAS Output Pin Select Bit (LCASS): Selects output pin for LCAS signal.
Bit 4
LCASS Description
0 Outputs LCAS signal from PF2 (Initial value)
1 Outputs LCAS signal from PF6
Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or
disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When
a pin is enabled for address output, the address is output regardless of the corresponding DDR
setting. When a pin is disabled for address output, it becomes an output port when the
corresponding DDR bit is set to 1.