Datasheet

Section 7 Bus Controller

Page 190 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Bit 5

RCDM Description

0 DRAM interface: selects RAS up mode (Initial value)

1 DRAM interface: selects RAS down mode

Bit 4—Reserved (CW2): Only write 0 to this bit.

Bits 3 and 2—Multiplex shift counts 1 and 0 (MXC1 and MXC0): These bits select the shift

amount to the low side of the row address of the multiplexed row/column address in DRAM

interface mode. They also select the row address to be compared in burst operation of the DRAM

interface.

Bit 3 Bit 2

MXC1 MXC0 Description

0 0 8-bit shift (Initial value)

(1) 8-bit access space: target row addresses for comparison are A23 to A8

(2) 16-bit access space: target row addresses for comparison are A23 to A9

1 9-bit shift

(1) 8-bit access space: target row addresses for comparison are A23 to A9

(2) 16-bit access space: target row addresses for comparison are A23 to A10

1 0 10-bit shift

(1) 8-bit access space: target row addresses for comparison are A23 to A10

(2) 16-bit access space: target row addresses for comparison are A23 to A11

1 —

Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1 and RLW0): These bits select the

number of wait states to be inserted in the CAS-before-RAS refresh cycle of the DRAM interface.

The selected number of wait states is applied to all areas set as DRAM space. Wait input via the

WAIT pin is disabled.

Bit 1 Bit 0

RLW1 RLW0 Description

0 0 Do not insert wait state (Initial value)

1 Insert 1 wait state

1 0 Insert 2 wait states

1 Insert 3 wait states