Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 191 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.2.8 DRAM Control Register (DRAMCR)
*
7
RFSHE
0
R/W
6
CBRM
0
R/W
5
RMODE
0
R/W
4
CMF
0
R/W
3
CMIE
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
R/W
:
:
:
The DRAMCR is an 8-bit read/write register that selects DRAM refresh mode, the refresh counter
clock, and sets the refresh timer control.
The DRAMCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Note: * This function is not available in the H8S/2695.
Bit 7—Refresh Control (RFSHE): This bit selects whether or not to perform refresh control.
When not performing refresh control, the refresh timer can be used as an interval timer.
Bit 7
RFSHE Description
0 Do not perform refresh control (Initial value)
1 Perform refresh control
Bit 6—CBR Refresh Mode (CBRM): This bit selects whether CBR refresh is performed in
parallel with other external access, or only CBR refresh is performed.
Bit 6
CBRM Description
0 Enables external access during CAS-before-RAS refresh (Initial value)
1 Disables external access during CAS-before-RAS refresh
Bit 5—Refresh Mode (RMODE): This bit selects whether or not to perform a self refresh in
software standby mode when performing refresh control (RFSHE=1).
Bit 5
RMODE Description
0 Do not perform self-refresh in software standby mode (Initial value)
1 Perform self-refresh in software standby mode