Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 203 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
8-Bit 3-State Access Space: Figure 7.7 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS
CSn
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
High impedance
Write
High
Note: n = 0 to 7
T
3
Figure 7.7 Bus Timing for 8-Bit 3-State Access Space