Datasheet

Section 7 Bus Controller
Page 208 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bus cycle
T
1
T
2
Address bus
φ
AS
CSn
RD
D15 to D8
Invalid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
High impedance
D7 to D0
Valid
Write
High
Note: n = 0 to 7
T
3
Figure 7.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)