Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 211 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Figure 7.14 shows an example of wait state insertion timing.
By program wait
T
1
Address bus
φ
AS
RD
Data bus
Read data
Read
HWR, LWR
Write data
Write
Note: indicates the timing of WAIT pin sampling.
WAIT
Data bus
T
2
T
w
T
w
T
w
T
3
By WAIT pin
Figure 7.14 Example of Wait State Insertion Timing
The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT
input disabled. At a manual reset, the bus control register values are retained and wait control
continues as before the reset.