Datasheet

Section 7 Bus Controller
Page 214 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.5.5 DRAM Interface Pins
Table 7.7 shows the pins used for the DRAM interface, and their functions.
Table 7.7 DRAM Interface Pin Configuration
Pin
In DRAM
Mode Name Direction Function
HWR WE Write enable Output Write enable when accessing
DRAM space in 2 CAS mode
LCAS LCAS Lower column address
strobe
Output Lower column address strobe signal
when accessing 16-bit DRAM space
CS2 RAS2 Row address strobe 2 Output Row address strobe when area 2
set as DRAM space
CS3 RAS3 Row address strobe 3 Output Row address strobe when area 3
set as DRAM space
CS4 RAS4 Row address strobe 4 Output Row address strobe when area 4
set as DRAM space
CS5 RAS5 Row address strobe 5 Output Row address strobe when area 5
set as DRAM space
CAS UCAS Upper column address
strobe
Output Upper column address strobe when
accessing DRAM space
WAIT WAIT Wait Input Wait request signal
A12 to A0 A12 to A0 Address pin Output Multiplexed output of row address
and column address
D15 to D0 D15 to D0 Data pin Input/output Data input/output pin
OE OE
*
Output enable pin Output Output enable signal when
accessing DRAM space in read
mode
Note: * Valid when OES bit set to 1.
7.5.6 Basic Timing
Figure 7.15 shows the basic access timing for DRAM space. There are four basic DRAM timing
states. In contrast to the standard bus interface, the corresponding ASTCR bit only controls the
enabling/disabling of wait insertion and has no effect on the number of access states. When the
corresponding ASTCR bit is cleared to 0, no wait states can be inserted in the DRAM access
cycle.