Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 215 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
The four basic timing states are as follows: T
P
(precharge cycle) 1 state, T
r
(row address output
cycle) 1 state, T
c1
and T
c2
(column address output cycle) two states.
When RCTS is set to 1, the CAS signal timing differs when reading and writing, being asserted Ω
cycle earlier when reading.
T
p
φ
CSn (RAS)
Read
Write
CAS, LCAS
CAS, LCAS
HWR (WE)
RD
AS
RD
D15 toD0
HWR (WE)
D15 to D0
A23 to A0
T
r
T
c1
T
c2
row column
Note: n = 2 to 5
RCTS= 1
RCTS= 0
Figure 7.15 Basic Access Timing