Datasheet

Section 7 Bus Controller
Page 216 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.5.7 Precharge State Control
When accessing DRAM, it is essential to secure a time for RAS precharging. In this LSI, it is
therefore necessary to insert 1 T
P
state when accessing DRAM space. By setting the TPC bit of the
MCR to 1, T
P
can be changed from 1 state to 2 states. Set the appropriate number of T
P
cycles
according to the type of DRAM connected and the operation frequency of the LSI. Figure 7.16
shows the timing when T
P
is set for 2 states.
Setting the TPC bit to 1 also sets the refresh cycle T
P
to 2 states.
T
p1
φ
Read
Write
D15 to D0
D15 to D0
A23 to A0
T
p2
T
r
T
c1
row column
T
c2
Note: n = 2 to 5
CSn (RAS)
CAS, LCAS
CAS, LCAS
HWR (WE)
HWR (WE)
RCTS = 0
RCTS = 1
Figure 7.16 Timing With Two Precharge Cycles