Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 217 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.5.8 Wait Control
There are two methods of inserting wait states in DRAM access: (1) insertion of program wait
states, and (2) insertion of pin waits via WAIT pin.
(1) Insertion of Program Wait States
Setting the ASTCR bit of an area set for DRAM to 1 automatically inserts from 0 to 3 wait states,
as set by WCRH and WCRL, between the T
c1
state and T
c2
state.
When a program wait is inserted, the write wait function is activated and only the CAS signal is
output only during the T
c2
state when writing.
Figure 7.17 shows example timing for the insertion of program waits.
Program
waits
T
p
Address bus
φ
CSn (RAS)
CAS, LCAS
Data bus
Read data
Read
CAS, LCAS
HWR (WE)
RD
AS
Write data
Write
Note: n = 2 to 5
Data bus
T
r
T
c1
T
w
T
w
T
c2
RCTS = 0
RCTS = 1
Figure 7.17 Example Program Wait Insertion Timing (Wait 2 State Insertion)