Datasheet

Section 7 Bus Controller
Page 218 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
(2) Insertion of Pin Waits
When the WAITE bit of BCRH is set to 1, wait input via the WAIT pin is valid regardless of the
ASTCR AST bit. In this state, a program wait is inserted when the DRAM space is accessed. If the
WAIT pin level is Low at the fall in φ in the final T
c1
or T
w
state, a further T
w
is inserted. If the
level of the WAIT pin is kept Low, T
w
is inserted until the level of the WAIT pin changes to High.
When wait states are inserted via the WAIT pin, the CAS when writing is output after the T
w
state.
Figure 7.18 shows example timing for the insertion of wait states via the WAIT pin.
WAIT pin wait states
Program
waits
T
p
Address bus
φ
CSn (RAS)
CAS, LCAS
Data bus
Read data
Read
CAS, LCAS
HWR (WE)
RD
AS
Write data
Write
Note: ↓ shows timing for WAIT pin sampling.
Data bus
T
r
T
c1
T
w
T
w
T
c2
n = 2 to 5
RCTS = 0
RCTS = 1
WAIT
Figure 7.18 Example Timing for Insertion of Wait States via WAIT Pin