Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 219 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.5.9 Byte Access Control
When 16-bit DRAMs are connected, the 2 CAS method can be used as the control signal required
for byte access.
Figure 7.19 shows the 2 CAS method control timing. Figure 7.20 shows an example of connecting
DRAM in high-speed page mode.
When all areas selected as DRAM space are set as 8-bit space, the LCAS pin functions as an I/O
port.
T
p
φ
CSn (RAS)
Byte control
A23 to A0
T
r
T
c1
T
c2
row
CAS
LCAS
HWR (WE)
column
Note: n = 2 to 5
Figure 7.19 2 CAS Method Control Timing (For High Byte Write Access)
When using DRAM EDO page mode, either use OE to control the read data or, as shown in figure
7.20, select RAS up mode. Figure 7.21 is an example of DRAM connection in EDO page mode
when OES=1.