Datasheet

Section 7 Bus Controller
Page 220 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
This LSI
(address shift set to 9 bits)
CS (RAS)
2CAS 4-Mbit DRAM
256 kbytes × 16-bit configuration
9-bit column address
OE
RAS
CAS UCAS
LCAS
LCAS
HWR (WE)
WE
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0 D15 to D0
(Row address input: A8 to A0)
(Column address input: A8 to A0)
Figure 7.20 High-speed Page Mode DRAM