Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 221 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
This LSI
(address shift set to 10 bits)
CS2 (RAS)
2CAS 16-Mbit DRAM
1 Mbyte × 16-bit configuration
10-bit column address
OE
RAS
CAS UCAS
LCAS
LCAS
HWR (WE)
CS3 (OE)
WE
A9
A8
A10
A9
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0 D15 to D0
(Row address input: A9 to A0)
(Column address input: A9 to A0)
Figure 7.21 Example Connection of EDO Page Mode DRAM (OES=1)
7.5.10 Burst Operation
In addition to full DRAM access (normal DRAM access), in which the row address is output each
time the data in DRAM is accessed, there is also a high-speed page mode that allows high-speed
access (burst access). In this method, if the same row address is accessed successively, the row
address is output once and then only the column address is changed. Burst access is selected by
setting the BE bit of the MCR to 1.