Datasheet

Section 7 Bus Controller
Page 222 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
(1) Operation Timing for Burst Access (High-Speed Page Mode)
Figure 7.22 shows the operation timing for burst access. When the DRAM space is successively
accessed, the CAS signal and column address output cycle (2 states) are continued as long as the
row address is the same in the preceding and succeeding access cycles. The MXC1 and MXC0
bits of the MCR specify which row address is compared.
T
p
φ
CSn (RAS)
Read
Write
CAS, LCAS
CAS, LCAS
AS
OE
OE
*
HWR (WE)
D15 to D0
HWR (WE)
D15 to D0
A23 to A0
T
r
T
c1
T
c2
row column1 column2
T
c1
T
c2
Notes: n = 2 to 5
* OE is enabled when OES = 1.
RCTS = 1
RCTS = 0
Figure 7.22 Operating Timing in High-Speed Page Mode
The bus cycle can also be extended in burst access by inserting wait states. The method and timing
of inserting the wait states is the same as in full access. For details, see section 7.5.8, Wait
Control.