Datasheet

Section 7 Bus Controller
Page 228 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
(2) Self-Refresh
One of the DRAM standby modes is the self-refresh mode (battery backup mode), in which the
DRAM generates its own refresh timing and refresh address.
To select self-refresh, set the RFSHE bit and RMODE bits of the DRAMCR to 1. Next, execute a
SLEEP instruction to make a transition to software standby mode. As shown in figure 7.29, the
CAS and RAS signals are output and the DRAM enters self-refresh mode.
When you exit software standby mode, the RMODE bit is cleared to 0 and self-refresh mode is
exited.
When making a transition to software standby mode, self-refresh mode starts after a CBR refresh,
providing there is a CBR refresh request. CBR refresh requests occurring immediately before
entering software standby mode are cleared on completion of the self-refresh when the software
standby mode is exited.
T
Rp
φ
T
Rcr
CAS, LCAS
Software standby
T
Rc3
HWR (WE)
CSn (RAS)
Note: n = 2 to 5
High level
Figure 7.29 Self-Refresh Timing