Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 229 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.6 DMAC Single Address Mode and DRAM Interface
(This function is not available in the H8S/2695)
When burst mode is set for the DRAM interface, the DDS bit selects the output timing for the
DACK signal. It also selects whether or not to perform burst access when accessing the DRAM
space in DMAC single address mode.
7.6.1 DDS=1
Burst access is performed on the basis of the address only, regardless of the bus master. The
DACK output level changes to Low afer the T
c1
state in the case of the DRAM interface.
Figure 7.30 shows the DACK output timing for the DRAM interface when DDS = 1.
T
p
φ
Read
Write
D15 to D0
D15 to D0
A23 to A0
T
r
T
c1
T
c2
row column
CSn (RAS)
CAS (UCAS)
LCAS (LCAS)
CAS (UCAS)
LCAS (LCAS)
DACK
HWR (WE)
HWR (WE)
RCTS = 1
RCTS = 0
Note: n = 2 to 5
Figure 7.30 DACK Output Timing when DDS=1 (Example Showing DRAM Access)