Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 233 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
T
1
Address bus
φ
CS0
AS
Data bus
T
2
T
1
T
1
Full access
RD
Burst access
Low address only changes
Read data Read data Read data
Figure 7.32 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)
7.7.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4.5, Wait
Control.
Wait states cannot be inserted in the burst cycle.