Datasheet

Section 7 Bus Controller
Page 234 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.8 Idle Cycle
7.8.1 Operation
When the H8S/2633 Group accesses external space, it can insert a 1-state idle cycle (T
I
) between
bus cycles in the following two cases: (1) when read accesses between different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 7.33 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B Bus cycle A Bus cycle B
Long output
floating time
Data
collision
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
T
1
Address bus
φ
RD
Data bus
T
2
T
3
T
I
T
1
T
2
CS (area A)
CS (area B)
CS (area A)
CS (area B)
Figure 7.33 Example of Idle Cycle Operation (1)