Datasheet

Section 7 Bus Controller
Page 236 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 7.35.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output
floating time
Data
collision
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
I
T
1
Bus cycle B
T
2
HWR
HWR
CS (area A)
CS (area B)
CS (area A)
CS (area B)
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 7.35 Relationship between Chip Select (CS) and Read (RD)