Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 237 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
(4) Notes
The setting of the ICIS0 and ICIS1 bits is invalid when accessing the DRAM space. For example,
if the 2nd of successive reads of different areas is a DRAM access, only the T
P
cycle is inserted,
not the T
1
cycle. Figure 7.36 shows the timing. Note, however, that ICIS0 and ICIS1 settings are
valid in burst access in RAS down mode, and an idle cycle is inserted. Figures 7.37 (a) and (b)
show the timing.
T
1
Address bus
φ
RD
External read
Data bus
T
2
T
3
T
p
T
r
DRAM space read
T
c1
T
c2
Figure 7.36 Example of DRAM Access after External Read
EXTAL
Address
RD
RAS
CAS, LCAS
Data bus
DRAM space read
T
p
T
r
T
c1
T
c2
T
1
T
1
T
2
T
3
T
c1
T
c1
T
c2
External read DRAM space read
Idle cycle
Figure 7.37 (a) Example Idle Cycle Operation in RAS Down Mode (ICIS1=1)