Datasheet

Section 7 Bus Controller
Page 238 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
EXTAL
Address
RD
HWR
RAS
CAS, LCAS
Data bus
DRAM space read
T
p
T
r
T
c1
T
c2
T
1
T
1
T
2
T
3
T
c1
T
c1
T
c2
External read DRAM space read
Idle cycle
Figure 7.37 (b) Example Idle Cycle Operation in RAS Down Mode (ICIS0=1)
7.8.2 Pin States in Idle Cycle
Table 7.8 shows pin states in an idle cycle.
Table 7.8 Pin States in Idle Cycle
Pins Pin State
A23 to A0 Contents of next bus cycle
D15 to D0 High impedance
CSn High
*
CAS High
AS High
RD High
HWR High
LWR High
DACKn High
Note: * Remains low in DRAM space RAS down mode or a refresh cycle.