Datasheet

Section 7 Bus Controller
Page 242 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
7.10.4 Transition Timing
Figure 7.39 shows the timing for transition to the bus-released state.
CPU
cycle
External bus released stateCPU cycle
Address
Minimum
1 state
T
0
T
1
T
2
φ
Address bus
HWR, LWR
BREQ
BACK
CSn
[1] [2] [3] [4] [5] [6]
Data bus
AS
RD
[1]
[2]
[3]
[4]
[5]
[6]
Note: * Output only when BREQOE is set to 1.
Low level of BREQ pin is sampled at rise of T
2
state.
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
BREQO signal goes high 1.5 clocks after BACK signal goes high.
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
BREQO*
Figure 7.39 Bus-Released State Transition Timing