Datasheet

Section 7 Bus Controller
R01UH0166EJ0600 Rev. 6.00 Page 243 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
φ
RAS
CAS
BREQ
BACK
A23 to A0
AS
CS
RD
DRAM space read access External bus released
Figure 7.40 Example Bus Release Transition Timing After DRAM Access (Reading
DRAM)
7.10.5 Notes
The external bus release function is deactivated when MSTPCR is set to H'FFFFFF or H'EFFFFF
and a transition is made to sleep mode. To use the external bus release function in sleep mode, do
not set MSTPCR to H'FFFFFF and H'EFFFFF.
When the CBRM bit is set to 1 to use the CBR refresh function, set the BREQ = 1 width greater
than the number of the slowest external access states. Otherwise, CBR refresh requests from the
refresh timer may not be performed.