Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 249 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
8.1.3 Overview of Functions
Tables 8.1 (1) and (2) summarize DMAC functions in short address mode and full address mode,
respectively.
Table 8.1 (1) Overview of DMAC Functions (Short Address Mode)
Address Register Bit Length
Transfer Mode Transfer Source Source Destination
Dual address mode
• Sequential mode
⎯ 1-byte or 1-word transfer
executed for one transfer request
⎯ Memory address
incremented/decremented by 1 or
2
⎯ 1 to 65536 transfers
• Idle mode
⎯ 1-byte or 1-word transfer
executed for one transfer request
⎯ Memory address fixed
⎯ 1 to 65536 transfers
• Repeat mode
⎯ 1-byte or 1-word transfer
executed for one transfer request
⎯ Memory address incremented/
decremented by 1 or 2
⎯ After specified number of
transfers (1 to 256), initial state is
restored and operation continues
• TPU channel 0 to
5 compare
match/input
capture A interrupt
• SCI transmit-data-
empty interrupt
• SCI reception
complete interrupt
• A/D converter
conversion end
interrupt
• External request
24/16 16/24
Single address mode
• 1-byte or 1-word transfer executed
for one transfer request
• Transfer in 1 bus cycle using DACK
pin in place of address specifying I/O
• Specifiable for sequential, idle, and
repeat modes
• External request
24/DACK DACK/24