Datasheet

Section 8 DMA Controller (DMAC)

(This function is not available in the H8S/2695)

R01UH0166EJ0600 Rev. 6.00 Page 259 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the

mode (sequential, idle, or repeat) in which transfer is to be performed.

Bit 5 DMABCR

RPE DTIE Description

0 0 Transfer in sequential mode (no transfer end interrupt) (Initial value)

1 Transfer in sequential mode (with transfer end interrupt)

1 0 Transfer in repeat mode (no transfer end interrupt)

1 Transfer in idle mode (with transfer end interrupt)

For details of operation in sequential, idle, and repeat mode, see section 8.5.2, Sequential Mode,

section 8.5.3, Idle Mode, and section 8.5.4, Repeat Mode.

Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR

to specify the data transfer direction (source or destination). The function of this bit is therefore

different in dual address mode and single address mode.

DMABCR Bit 4

SAE DTDIR Description

0 0 Transfer with MAR as source address and IOAR as destination

address (Initial value)

1 Transfer with IOAR as source address and MAR as destination address

1 0 Transfer with MAR as source address and DACK pin as write strobe

1 Transfer with DACK pin as read strobe and MAR as destination address