Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
Page 266 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A.
Bit 6
DTE1A Description
0 Data transfer disabled (Initial value)
1 Data transfer enabled
Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B.
Bit 5
DTE0B Description
0 Data transfer disabled (Initial value)
1 Data transfer enabled
Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A.
Bit 4
DTE0A Description
0 Data transfer disabled (Initial value)
1 Data transfer enabled
Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an
interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request
to the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.