Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
Page 270 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
(2) Block Transfer Mode
ETCRA
Holds block size
Bit : 15 14 13 12 11 10 9 8
ETCRAH :
Initial value : * * * * * * * *
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Block size counter
Bit : 7 6 5 4 3 2 1 0
ETCRAL :
Initial value : * * * * * * * *
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
ETCRB
Block Transfer Counter
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETCRB :
Initial value : * * * * * * * * * * * * * * * *
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the
block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when
the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block
size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any
desired number of bytes or words.
ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.