Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 275 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
8.3.5 DMA Band Control Register (DMABCR)
Bit : 15 14 13 12 11 10 9 8
DMABCRH : FAE1 FAE0 — — DTA1 — DTA0 —
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 7 6 5 4 3 2 1 0
DMABCRL : DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC
channel.
DMABCR is initialized to H'0000 by a reset, and in standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are used together as a single channel.
Bit 15
FAE1 Description
0 Short address mode (Initial value)
1 Full address mode
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are used together as a single channel.
Bit 14
FAE0 Description
0 Short address mode (Initial value)
1 Full address mode