Datasheet

Section 8 DMA Controller (DMAC)

(This function is not available in the H8S/2695)

R01UH0166EJ0600 Rev. 6.00 Page 279 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt

handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.

Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1

transfer break interrupt.

Bit 3

DTIE1B Description

0 Transfer break interrupt disabled (Initial value)

1 Transfer break interrupt enabled

Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0

transfer break interrupt.

Bit 1

DTIE0B Description

0 Transfer break interrupt disabled (Initial value)

1 Transfer break interrupt enabled

Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable

an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the

DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request

to the CPU or DTC.

A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt

handling routine, or by performing processing to continue transfer by setting the transfer counter

and address register again, and then setting the DTE bit to 1.

Bit 2—Data Transfer End Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1

transfer end interrupt.

Bit 2

DTIE1A Description

0 Transfer end interrupt disabled (Initial value)

1 Transfer end interrupt enabled