Datasheet

Section 8 DMA Controller (DMAC)

(This function is not available in the H8S/2695)

Page 280 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Bit 0—Data Transfer End Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0

transfer end interrupt.

Bit 0

DTIE0A Description

0 Transfer end interrupt disabled (Initial value)

1 Transfer end interrupt enabled

8.4 Register Descriptions (3)

8.4.1 DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the

transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions

so that only specific bits of DMACR for the specific channel and also DMATCR and DMABCR

can be changed to prevent inadvertent changes being made to registers other than those for the

channel concerned. The restrictions applied by DMAWER are valid for the DTC.

Figure 8.2 shows the transfer areas for activating the DTC with a channel 0A transfer end

interrupt, and reactivating channel 0A. The address register and count register area is re-set by the

first DTC transfer, then the control register area is re-set by the second DTC chain transfer.

When re-setting the control register area, perform masking by setting bits in DMAWER to prevent

modification of the contents of the other channels.